Random access memory device utilizing a vertically oriented select transistor

ABSTRACT

A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

RELATED APPLICATIONS

[0001] This application is a continuation-in-part of U.S. patentapplication Ser. No. 10/230,568 filed Aug. 29, 2002, the disclosure ofwhich is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to memory devices, and morespecifically, to random access memory devices having vertical accesstransistors.

[0004] 2. Description of the Related Art

[0005] Semiconductor memory devices are widely used for storing data insystems such as computer systems. Random access memory devices includedynamic random access memory (DRAM), magnetic random access memory(MRAM) and programmable conductor random access memory (PCRAM) memorycells that are being developed for non-volatile data storage incomputers and other information processing devices.

[0006] A DRAM cell typically includes an access device, such as a fieldeffect transistor (FET), which is coupled to a storage device, such as acapacitor. The access device allows the transfer of charges to and fromthe storage capacitor, thereby facilitating read and write operations inthe memory cell. The memory cells typically are arranged in a number ofrows and columns to provide a memory array. DRAM cells require continualrefreshing.

[0007] Recent developments in memory include MRAM and PCRAM devices.MRAM memory cells are vertical stacks of thin films with certainmagnetic and conductive interactive properties. An array of these cellsforms a row and column addressable memory array. Bitwise information isstored in each cell based on the relative orientation of magneticmoments in thin films of the cell. Magnetic tunnel junctions areexamples of the type of thin film structures used in magnetic memorycells.

[0008] A PCRAM memory cell utilizes silver electromigration through aglass to form a contact when an electrical potential is applied acrossthe plates of the cell. The contact may be broken by reversing thepolarity of the potential and allowing reverse current to flow until thesilver migrates back and breaks the connection.

[0009] MRAM and PCRAM do not require dynamic refreshing as does DRAM,and can be implemented without using a cell access transistor.Accordingly, MRAM arrays can be produced more efficiently (more bits perunit area) than DRAM. The lack of an access transistor, however, exposesMRAM cells to “sneak” currents through unselected cells, which requirescompensation by sense circuitry in order to isolate the selected MRAMcell.

[0010] Memory cells, such as MRAM and PCRAM cells, would benefit fromhaving an access transistor that would allow array efficiency to bepreserved, while providing current isolation of the cells.

[0011] With the constantly increasing demand for higher data storagecapacity, memory arrays are becoming more dense. Memory densitytypically is limited by current processing technologies used forfabricating the memory arrays. Thus, it also is desirable to increasememory density.

BRIEF SUMMARY OF THE INVENTION

[0012] The present invention provides higher density memory arrays usingvertical technology in fabricating the access transistors to providememory bits with minimal leakage, thereby preventing the loss of storagecell data while preserving array efficiency. Further, alpha-particleinduced soft errors that alter the data stored in the memory cells arereduced and simplified fabrication techniques also are provided.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The foregoing and other advantages ofthe invention will becomemore apparent from the detailed description of exemplary embodimentsprovided below with reference to the accompanying drawings in which:

[0014]FIG. 1 is a partial schematic illustrating an integrated memorydevice circuit according to the present invention;

[0015] FIGS. 2-10 illustrate steps in the fabrication of memory bitsaccording to an exemplary embodiment of the present invention;

[0016]FIG. 11 illustrates an alternative embodiment of forming a bitline in a memory bit according to the present invention;

[0017]FIG. 12 is an alternative view of the bit line of FIG. 11;

[0018]FIG. 13 is a cross-sectional view of the bit line shown in FIGS.11 and 12; and

[0019]FIG. 14 illustrates an alternative form of a word line in a memorybit according to the present invention;

[0020]FIG. 15 is a cross-sectional view of the word line structure ofFIG. 14; and

[0021]FIG. 16 is a processor system including memory device according tothe embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0022] One or more specific embodiments of the present invention will bedescribed below. In an effort to provide a concise description of theseembodiments, not all features of an actual implementation are describedin the specification. It should be appreciated that in the developmentof any such actual implementation, as in any engineering or designproject, numerous implementation-specific decisions must be made toachieve the developers' specific goals, such as compliance withsystem-related and business-related constraints, which may vary from oneimplementation to another. Moreover, it should be appreciated that sucha development effort might be complex and time consuming, but wouldnevertheless be a routine undertaking of design, fabrication, andmanufacture for those of ordinary skill having the benefit of thisdisclosure.

[0023] The terms “wafer” and “substrate” are to be understood asinterchangeable and as including silicon, silicon-on-insulator (SOI) orsilicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxiallayers of silicon supported by a base semiconductor foundation, andother semiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processsteps may have been utilized to form regions, junctions or materiallayers in or on the base semiconductor structure or foundation. Inaddition, the semiconductor need not be silicon-based, but could bebased on silicon-germanium, germanium, gallium arsenide, or other knownsemiconductor materials.

[0024]FIG. 1 is a partial schematic illustrating an integrated circuit,such as a memory device 10, incorporating an array of memory cells whichmay be fabricated in accordance with an exemplary embodiment of thepresent invention. The memory device 10 may be an MRAM device or a PCRAMdevice, for example. In the exemplary embodiment, the memory device 10includes a number of memory bits 12 arranged in a grid patterncomprising a number of rows and columns. As can be appreciated, thenumber of memory cells (and corresponding rows and columns) may varydepending on system requirements and fabrication technology. Each memorybit 12 indudes an access device and a storage device. In the presentexemplary embodiment, the access device comprises a field-effecttransistor (FET) 14 and the storage device comprises memory cell 16. Theaccess device 14 is implemented to provide controlled access to thememory cell 16. In the exemplary memory bit 12, the FET 14 includes adrain terminal 18 and a source terminal 20, along with a gate terminal22 for controlling conduction between the drain and source terminals18,20. The memory cell 16 is coupled between one of the source/drainterminals 18, 20 and a reference voltage (illustrated as a groundpotential).

[0025] It should be noted that although the above description depictsthe terminal of the access device that is coupled to the memory cell 16as the source 20 and the other non-gate terminal of the access device asthe drain 18, during read and write operations, the FET 14 may beoperated such that each of the terminals 18, 20 operates at one time oranother as a source or a drain. Accordingly, for purposes of furtherdiscussion, it should be recognized that whenever a terminal isidentified as a source or a drain, it is only for convenience purposes.Thus, during operation of the FET 14 either terminal could be a sourceor a drain depending on the manner in which the FET 14 is beingcontrolled by the voltages applied to the terminals 18, 20, 22 of theFET 14.

[0026] As previously described, the memory array of device 10 isarranged in a series of rows and columns. To implement data storagecapabilities in each memory bit 12, an electrical charge is placed onthe drain 18 of the FET 14 via a corresponding bitline (BL). Bycontrolling the voltage at the gate 22 via the wordline (WL), a voltagepotential may be created across the FET 14 such that the electricalcharge at the drain 18 can flow to the memory cell 16.

[0027] The bitlines BL are used to read from, and write data to, thememory bits 12. The wordlines WL are used to activate the FET 14 toaccess a particular row of memory bits 12. The memory device 10 includesan address buffer 24, a row decoder 26, and column decoder 28 to controlthe wordlines WL and bitlines BL. The address buffer 24 controls the rowdecoder 26 and the column decoder 28 such that the row decoder 26 andcolumn decoder 28 selectively access memory bits 12 in response toaddress signals provided on the address bus 30 during read and writeoperations. The address signals are typically provided by an externalcontroller such as a microprocessor or other memory controller. Thecolumn decoder 28 may also include sense amplifiers and input/outputcircuitry to further enable data to be read from and written to thememory bits 12 via the bitlines BL.

[0028] In one exemplary mode of operation, the memory device 10 receivesan address of a particular memory bit 12 at the address buffer 24. Theaddress buffer 24 passes a row address to the row decoder 26 and acolumn address to the column decoder 28. The row decoder 26 selectivelyactivates a particular wordline WL to activate the FETs 14 of eachmemory bit 12 connected to the selected wordline WL. The column decoder28 selects the bitline (or bitlines) BL of the memory bit 12corresponding to the requested column address. For a write operation,data received by input/output circuitry is coupled to the selectedbitline (or bitlines) BL and is stored in memory cell 16 through the FET14. The information corresponds to binary data (i.e., a logical “1” or“0”). For a read operation, data stored in the selected memory bit 12,represented by the potential state stored in the memory cell 16, iscoupled to the selected bitline (or bitlines) BL and amplified by thesense amplifier; a corresponding output is provided to the input/outputcircuit in the column decoder 28.

[0029] The memory array of the memory device 10 may be fabricated usinga variety of technologies. One particularly advantageous technique forfabricating the memory bits 12 is now described with reference to FIGS.2-10. To provide a high density memory device 10, the channel of the FET14 is fabricated perpendicular to the surface of a wafer (i.e.,vertically-oriented) rather than parallel to the surface.Advantageously, the vertically-oriented access FET 14 occupies lessspace than would be occupied by FETs produced by other techniques.

[0030] In addition, by incorporating vertically-oriented access FETs 14,the memory bits 12 are less susceptible to alpha-radiation. The memorybits 12 have increased radiation hardness, and reduced potential forsoft errors imparted by alpha particles produced, for example, frompackaging materials, over bits with a non-vertically oriented access FET14.

[0031]FIG. 2 illustrates a semiconductor substrate 32, made of materialsuch as silicon (Si). More specifically, the substrate 32 is a P-dopedsilicon. To fabricate the vertically oriented access FETs 14, thesubstrate 32 is subtractively etched to produce silicon pillars 33. Asdescribed further below, the pillars 33 will eventually form thechannels of the FETs 14. The pillars 33 may be formed through any one ofa number or commonly known etching techniques, such as plasma etching,ion beam etching, or reactive ion etching (RIE). Each pillar 33 has aheight of approximately 2.0 μm and a diameter of approximately 0.2 μm,for example. In the present embodiment, each pillar 33 may be generallycylindrical such that the top view of each pillar 33 is generallycircular. This shape facilitates the eventual fabrication of annularrings around the pillars 33, as described further below. Alternatively,pillars having other geometric cross-sectional shapes, such asrectangles, squares, or ellipses, may be implemented to construct thechannel of the FETs 14.

[0032] As can be appreciated, the specific heights and thicknesses ofthe features and materials described herein are exemplary in nature andfor purposes of illustration. Accordingly, the exemplary dimensionsprovided herein are in no way meant to limit the scope of the presentinvention. Further, while the present exemplary embodiment illustratespillars 33 that are perpendicular to the surface of the substrate 32,the pillars 33 may extend away from the surface of the substrate 32 atother angles. For instance, in an alternate embodiment, the pillars 33may be fabricated at an angle in the range of approximately 45° toapproximately 90° with respect to the surface of the substrate 32.

[0033] After formation of the pillars 33, an isolation layer, such as anoxide layer 34, is applied on top of the substrate 32, as illustrated inFIG. 3. The isolation layer can include any number of non-conductivematerials such as oxide, silicon dioxide, silicon nitride, etc. Theoxide layer 34 is applied by chemical vapor deposition (CVD), forexample. The oxide layer 34 is disposed at a thickness of approximately0.2 μm. As can be appreciated by those skilled in the art, the oxidelayer 34 is disposed over the entire surface of the substrate 32. Aphotoresist is used to facilitate the patterning and etching of theoxide layer 34 such that the oxide layer 34 is not present on top of thepillars 33. It should be understood that those skilled in the artreadily understand the deposition, masking, and etching techniques usedto construct the patterns illustrated with reference to FIGS. 2-10.

[0034]FIG. 4 illustrates the deposition of the material used to createthe bitlines BL discussed previously with respect to FIG. 1. Apolysilicon layer 36 is disposed on the oxide layer 34. The polysiliconlayer 36 can be over-doped such that when the substrate 32 is baked orotherwise heated, the concentration gradient between the polysiliconlayer 36 and the substrate 32 will cause dopants to diffuse from thepolysilicon layer 36 into the substrate 32, forming n+ contact regions38 at the silicon/polysilicon interface as illustrated in FIG. 4. Thesilicon/polysilicon interface generally is near the base of the pillar33, where the n+ contact regions 38 are formed by so-called“out-diffusion.” The contact regions 38 may also be formed using gasdiffusion or ion implant techniques. The polysilicon layer 36 may bedisposed at a thickness of approximately 0.4 μm, for example.

[0035]FIG. 5 illustrates a cross-sectional top view of the structureillustrated with reference to FIG. 4 taken along cut lines 5-5. Thepolysilicon layer 36 is patterned to provide annular rings around thesilicon pillars 33. Thus, the polysilicon layer 36, which forms thebitlines BL of the memory array (described with reference to FIG. 1),extends to connect all of the silicon pillars 33 in a given column ofthe array. As previously described, the silicon pillar 33 also includesn+ contact regions 38 formed from the polysilicon layer 36. Advantagesof the annular ring pattern around the silicon pillars 33 used to formthe bitline polysilicon layer 36, are discussed below.

[0036] Referring to FIG. 6, after deposition of the polysilicon layer 36and the formation of the n+ contact regions 38, another isolation layer,such as an oxide layer 40, is disposed on the polysilicon layer 36. Theoxide layer 40 electrically isolates the polysilicon layer 36 fromlayers subsequently disposed over the oxide layer 40. As with the oxidelayer 34, the oxide layer 40 is deposited, patterned and etched toprovide a structure as illustrated in FIG. 6. The thickness of the oxidelayer 36 may be approximately 0.2 μm, for example.

[0037]FIG. 6 further illustrates a thin gate oxide layer 42 which isdisposed or grown around the pillar 33 to facilitate the functionalityof the gate 22 (FIG. 1) of the FET 14. The gate oxide layer 42 may begrown to a thickness of approximately 60 angstroms by any one of anumber of conventional techniques. It should be noted that for purposesof etch selectivity, the oxide layer 40 and the gate oxide 42 maycomprise different insulated materials with respect to one another, suchas oxide, silicon dioxide, silicon nitride, TEOS, etc.

[0038] Referring to FIGS. 7 and 8, after the deposition of the oxidelayer 40 and the growth of the gate oxide layer 42, another layer ofpolysilicon is deposited, patterned, and etched to form the wordlinepolysilicon layer 44. The thickness of the wordline polysilicon layer 44extending upwardly from the surface of the substrate 32 in the directionof the pillar 33 may be about 0.8 μm, for example. The thickness of thewordline polysilicon layer 44 extending outwardly from the surface ofthe pillar 33 may be about 0.1 to about 0.2 μm, for example. Thewordline polysilicon layer 44 is patterned such that the polysiliconmaterial completely surrounds the pillar 33. As illustrated in FIG. 8,the wordline polysilicon layer 44 is patterned such that it runsperpendicular to the bitline polysilicon layer 36. The advantages of theannular ring pattern around the silicon pillars 33 used to form thewordline polysilicon layer 44 will be discussed further below.

[0039] Referring to FIG. 9, after the deposition, patterning, andetching of the wordline polysilicon layer 44, a dielectric layer 46,such as silicon dioxide or silicon nitride, is deposited over the entirestructure such that each pillar 33 is covered completely with dielectricmaterial. The dielectric layer 46 may be disposed by chemical vapordeposition (CVD), for example. Thus, the dielectric layer 46 may bedeposited to a thickness of more than 1.0 μm, in the present exemplaryembodiment, such that the dielectric layer 46 is deposited to a heightapproximately coplanar with the height of the pillars 33.

[0040] After deposition of the dielectric layer 46, the surface of thestructure may be planarized such as by chemical-mechanicalpolishing/planarization (CMP). The surface of the structure isplanarized to a point where the thin gate oxide layer 42 is removed fromthe top of the pillar 33 thereby exposing the silicon pillar 33.Finally, an n+ contact region 48 is formed at the top of the pillar 33.The n+ contact region 48 may be formed through gas diffusion or ionimplant techniques, for example. The n+ contact region 48 forms thesource 20 (FIG. 1) that will be coupled to the memory cell 16 formed insubsequent processing steps discussed below and illustrated with respectto FIG. 10.

[0041] The completed access device (FET 14) is illustrated in FIG. 9.The silicon pillar 33 forms a channel of the FET 14. By completelysurrounding the channel (i.e., pillar 33) with the wordline polysiliconlayer 44, the gate 22 (FIG. 1) functions as a channel with increaseddrive capabilities over access devices having conventional gatestructures. The annular structure of the bitline polysilicon layer 36offers advantages of compact layout and efficiency.

[0042] To complete the memory bit 12 (FIG. 1), a storage device, such asthe memory cell 16, is fabricated. FIG. 10 illustrates a completedmemory bit structure 12 incorporating an exemplary memory cell 16.

[0043] One technique for fabricating the memory cell 16 begins bydisposing a sacrificial oxide layer (not shown) on top of the structuredescribed above and illustrated with reference to FIG. 9. The oxidelayer is disposed at a thickness at least as high as what later will bethe height or vertical thickness of the memory cell 16. For instance,the thickness of the sacrificial oxide may be approximately 2.0 μm. Oncethe sacrificial oxide is deposited, holes are drilled or etched in theoxide to create wells which are vertical with respect to the surface ofthe substrate. After the wells are created, the layers making up thememory cell 16 may be disposed in the wells. A lowest layer 50 isdeposited to make contact with the n+ contact region 48 of the pillar33. This interface provides the connection of the FET 14 to the memorycell 16.

[0044] Memory cell 16 can be fabricated by various methods, depending onthe type of memory cell used in the memory device 10. An MRAM cellgenerally will include a free magnetic layer, a pinned magnetic layer,and a magnetic tunnel junction barrier disposed between the two magneticlayers. A description of MRAM cells in general, and an exemplary methodof fabricating MRAM cells, are disclosed in U.S. Pat. No. 6,358,756,issued Mar. 19, 2002 and of common assignment with the presentinvention, the entire disclosure of which is incorporated herein byreference.

[0045] Memory cell 16 also can be a PCRAM cell. A PCRAM cell generallywill include a lower contact layer on which is disposed a PCRAM bit.PCRAM bits are resistance variable memory elements in which a metalcontaining layer is formed between a first chalcogenide glass layer anda second glass layer. One or both of the glass layers may be doped witha metal and one or more metal containing layers may be provided betweenthe glass layers. An exemplary method of manufacturing a PCRAM cell isdisclosed in pending U.S. patent application Ser. No. 10/120,521, filedApr. 12, 2002 and of common assignment with the present invention, theentire disclosure of which is incorporated herein by reference.

[0046]FIG. 11 illustrates a bitline BL according to another embodimentof the invention. More specifically, FIG. 11 illustrates across-sectional top view of an alternate embodiment of the structureillustrated with reference to FIG. 4 taken along cut lines 5-5. As canbe seen, a polysilicon layer 36A is patterned to provide semi-annularrings around the silicon pillars 33. The polysilicon layer 36A, whichforms the bitlines of the memory array described with reference to FIG.1, extends to connect each of the silicon pillars 33 in a single column.As previously described, the silicon pillar 33 also includes n+ contactregions 38A which may be formed by out diffusion from the polysiliconlayer 36A. Thus, the present exemplary embodiment provides a polysiliconlayer 36A which is patterned to surround only a portion of the pillar33. Advantageously, the alternate exemplary embodiment illustrated withreference to FIG. 11 may provide for further pitch reduction and thus,reduction in the area of each memory bit and overall die size.

[0047] Similarly, the wordline WL, may be patterned to provide asemi-annular ring. FIGS. 12 and 13 illustrate an alternate embodiment ofthe wordline WL, incorporating semi-annular rings. FIG. 12 illustratesan alternative view of the structure illustrated in FIG. 7. Thus, afterthe deposition of the oxide layer 40 and the growth of the gate oxidelayer 42, a polysilicon layer is disposed, patterned and etched to formthe polysilicon layer 44A having semi-annular rings. The wordlinepolysilicon layer 44A extends in a direction perpendicular to the pageand thus, the view of the structure illustrated in FIG. 12 includes thepolysilicon layer 44A on only one side of the pillar 33. However, thewordline polysilicon layer 44A is patterned about a portion of thepillar 33, as further illustrated with respect to FIG. 13.

[0048]FIG. 13 illustrates a cross-sectional top view of the alternateembodiment illustrated in FIG. 12 taken along cut line 13-13. As can beseen, the wordline polysilicon layer 44A is patterned to providesemi-annular rings around the silicon pillars 33. The wordlinepolysilicon layer 44A is patterned such that it runs perpendicular tothe bitline polysilicon layer 36. The semi-annular wordline polysiliconlayer 44A may be implemented along with the semi-annular bitlinepolysilicon layer 36A described with reference to FIG. 11. Further,while FIGS. 11-13 illustrate semi-annular rings, it should be evidentthat an annular ring may extend around any desirable portion (e.g., morethan or less than half) of the pillar 33. For instance, it may beadvantageous to provide annular rings that extend around only a quarterto a third of the circumference of the pillar 33. Alternatively, it maybe advantageous to provide annular rings that extend around two-thirdsto three-quarters of the circumference of the pillar 33, for example.

[0049]FIG. 14 illustrates an alternate embodiment of the structureillustrated in FIG. 9, implementing an alternate technique forfabricating the wordline WL. FIG. 15 illustrates a cross-sectional topview of the alternate embodiment illustrated in FIG. 14 taken along thecut line 15-15. In the present exemplary embodiment, the wordlinepolysilicon layer 44 is replaced with a thin gate conductor layer 44Band a thick signal conductor layer 44C. As can be seen, the thin gateconductor layer 44B completely surrounds the pillar 33. The thin gateconductor layer 44B may have a thickness extending from the surface ofthe pillar 33 of less than 0.1 μm, for example. After the deposition,patterning and etching of the thin conductor layer 44B, a dielectriclayer 46A may be disposed. Unlike the embodiment illustrated in FIG. 9,however, the dielectric layer 46A is not disposed to cover the entirepillar 33. The dielectric layer 46A is disposed such that a portion ofthe pillar remains uncovered, as illustrated in FIG. 14.

[0050] Next, the thick signal conductor layer 44C is disposed, patternedand etched to form the wordline WL. The gate conductor layer 44B iselectrically coupled to the signal conductor layer 44C. In one exemplaryembodiment, the gate conductor layer 44B and the signal conductor layer44C are each polysilicon layers. However, as can be appreciated, thegate conductor layer 44B and the signal conductor layer 44C may bedifferent materials. For instance, the gate conductor layer 44B may be apolysilicon layer, while the signal conductor layer 44C may be atungsten layer. To complete the structure, a dielectric layer 46B may bedisposed to a thickness sufficient to cover the pillars 33, and thesurface of the structure may be planarized, as previously described.Advantageously, by providing a thin gate conductor layer 44B coupled toa thick signal conductor layer 44C, a smaller pitch between structuresmay be implemented, thereby reducing cell size and overall die size.

[0051] As can be appreciated, while the present wordline and bitlinestructures are described as being fabricated through depositiontechniques, other processes, such as a damascene process may implementedto form the wordlines and bitlines in accordance with the presenttechniques. Further, while the present exemplary embodiments haveillustrated the annular gate structures with respect to DRAM memorydevices, the present techniques may be implemented in a number of otherapplications, such as flash memory cells, SRAM memory cells, anti-fusedevices, image sensors and simple logic gates, for example.

[0052]FIG. 16 illustrates an exemplary processing system 900, which mayincorporate memory devices 10 of the present invention into one of moreof the memory modules 908 described below. The processing system 900includes one or more processors 901 coupled to a local bus 904. A memorycontroller 902 and a primary bus bridge 903 also are coupled to localbus 904. The processing system 900 may include multiple memorycontrollers 902 and/or multiple primary bus bridges 903. The memorycontroller 902 and the primary bus bridge 903 may be integrated as asingle device 906.

[0053] The memory controller 902 is also coupled to one or more memorybuses 907. Each memory bus accepts memory components 908. The memorycomponents 908 may be a memory card or a memory module. Examples ofmemory modules include single inline memory modules (SIMMs) and dualinline memory modules (DIMMs). The memory components 908 may include oneor more additional devices 909. For example, in a SIMM or DIMM, theadditional device 909 might be a configuration memory, such as a serialpresence detect (SPD) memory. The memory controller 902 may also becoupled to a cache memory 905. The cache memory 905 may be the onlycache memory in the processing system. Alternatively, other devices, forexample, processors 901 may also include cache memories, which may forma cache hierarchy with cache memory 905. If the processing system 900include peripherals or controllers which are bus masters or whichsupport direct memory access (DMA), the memory controller 902 mayimplement a cache coherency protocol. If the memory controller 902 iscoupled to a plurality of memory buses 907, each memory bus 907 may beoperated in parallel, or different address ranges may be mapped todifferent memory buses 907.

[0054] The primary bus bridge 903 is coupled to at least one peripheralbus 910. Various devices, such as peripherals or additional bus bridgesmay be coupled to the peripheral bus 910. These devices may include astorage controller 911, a miscellaneous I/O device 914, a secondary busbridge 915 communicating with a secondary bus 916, a multimediaprocessor 918, and a legacy device interface 920. The primary bus bridge903 may also coupled to one or more special purpose high speed ports922. In a personal computer, for example, the special purpose port mightbe the Accelerated Graphics Port (AGP), used to couple a highperformance video card to the processing system 900.

[0055] The storage controller 911 couples one or more storage devices913, via a storage bus 912, to the peripheral bus 910. For example, thestorage controller 911 may be a SCSI controller and storage devices 913may be SCSI discs. The I/O device 914 may be any sort of peripheral. Forexample, the I/O device 914 may be a local area network interface, suchas an Ethernet card. The secondary bus bridge 915 may be used tointerface additional devices via another bus to the processing system.For example, the secondary bus bridge may be an universal serial port(USB) controller used to couple USB devices 917 via to the processingsystem 900. The multimedia processor 918 may be a sound card, a videocapture card, or any other type of media interface, which may also becoupled to one additional devices such as speakers 919. The legacydevice interface 920 is used to couple at least one legacy device 921,for example, older styled keyboards and mice, to the processing system900.

[0056] The processing system 900 illustrated in FIG. 16 is only anexemplary processing system with which the invention may be used. WhileFIG. 16 illustrates a processing architecture especially suitable for ageneral purpose computer, such as a personal computer or a workstation,it should be recognized that well known modifications can be made toconfigure the processing system 900 to become more suitable for use in avariety of applications. For example, many electronic devices whichrequire processing may be implemented using a simpler architecture whichrelies on a CPU 901 coupled to memory components 908. These electronicdevices may include, but are not limited to audio/video processors andrecorders, gaming consoles, digital television sets, wired or wirelesstelephones, navigation devices (including system based on the globalpositioning system (GPS) and/or inertial navigation), and digitalcameras and/or recorders. The modifications may include, for example,elimination of unnecessary components, addition of specialized devicesor circuits, and/or integration of a plurality of devices.

[0057] While the invention may be susceptible to various modificationsand alternative forms, specific embodiments have been shown by way ofexample in the drawings and have been described in detail herein.However, it should be understood that the invention is not intended tobe limited to the particular forms disclosed. Rather, the invention isto cover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the followingappended claims.

What is claimed is:
 1. An integrated circuit device comprising: asubstrate having a surface; a pillar of semiconductor material extendingfrom the substrate surface and having a first doped region formed in thesemiconductor material at a first end of the pillar and having a seconddoped region formed in the semiconductor material at a second end of thepillar, the pillar being configured to form the channel of a transistor;a first annular ring disposed about at least a portion of the pillar,wherein the first annular ring comprises a conductive material; and amemory bit in electrical contact with the first doped region.
 2. Theintegrated circuit device, as set forth in claim 1, wherein the pillarcomprises silicon.
 3. The integrated circuit device, as set forth inclaim 1, wherein the pillar has a circular cross-section.
 4. Theintegrated circuit device, as set forth in claim 1, wherein the pillarhas a square-shaped cross-section.
 5. The integrated circuit device, asset forth in claim 1, wherein the pillar extends in a directionapproximately perpendicular to the substrate surface.
 6. The integratedcircuit device, as set forth in claim 1, wherein the first annular ringcomprises polycrystalline silicon.
 7. The integrated circuit device, asset forth in claim 1, wherein the first doped region is configured toform one of a drain and source of the transistor and wherein the seconddoped region is configured to form the other of the drain and source ofthe transistor.
 8. The integrated circuit device, as set forth in claim7, wherein the first annular ring is configured to form the gate of thetransistor and further configured to induce conduction through thepillar between the first doped region and the second doped region when avoltage is applied to the first annular ring.
 9. The integrated circuitdevice, as set forth in claim 8, wherein the first annular ring iscoupled to a wordline of a memory array.
 10. The integrated circuitdevice, as set forth in claim 1, wherein the first annular ring isdisposed about the pillar forming a continuous ring thereabout.
 11. Theintegrated circuit device, as set forth in claim 1, wherein the firstannular ring is disposed about approximately half of the pillar forminga semi-annular ring thereabout.
 12. The integrated circuit device, asset forth in claim 1, wherein the first annular ring comprises apolycrystalline material.
 13. The integrated circuit device, as setforth in claim 8, comprising a second annular ring disposed about atleast a portion of the pillar, wherein the second annular ring iselectrically isolated from the first annular ring, and wherein thesecond annular ring comprises a conductive material.
 14. The integratedcircuit device, as set forth in claim 13, wherein the second annularring is more proximate to the substrate surface than the first annularring.
 15. The integrated circuit device, as set forth in claim 13,wherein the second annular ring is disposed directly adjacent to thesecond doped region.
 16. The integrated circuit device, as set forth inclaim 13, wherein an oxide layer is coupled between the first annularring and the second annular ring.
 17. The integrated circuit device, asset forth in claim 13, wherein the second annular ring is coupled to abitline of a memory array.
 18. The integrated circuit device, as setforth in claim 13, wherein the second annular ring is disposed about thepillar forming a continuous ring thereabout.
 19. The integrated circuitdevice, as set forth in claim 13, wherein the second annular ring isdisposed about approximately half of the pillar forming a semi-annularring thereabout.
 20. The integrated circuit device, as set forth inclaim 1, wherein the memory bit is a magnetic storage device.
 21. Theintegrated circuit device, as set forth in claim 20, wherein the storagedevice comprises a magnetic tunnel junction.
 22. The integrated storagedevice, as set forth in claim 1, wherein the memory bit is a PCRAMdevice.
 23. A memory device comprising: a non-volatile memory storagedevice; and an access transistor coupled to the storage device, saidaccess transistor comprises: a vertical channel coupled between a firstsource/drain and a second source/drain; and a ring-like gate regiondisposed about at least a portion of the vertical channel and configuredto initiate conduction between the first source/drain and the secondsource/drain.
 24. The memory device, as set forth in claim 23, whereinthe storage device comprises a magnetic tunnel junction.
 25. The memorydevice, as set forth in claim 23, wherein the vertical channel comprisessilicon (Si).
 26. The memory device, as set forth in claim 23, whereinthe gate region comprises polysilicon.
 27. The memory device, as setforth in claim 23, wherein the gate region comprises a circular ring.28. The memory device, as set forth in claim 23, wherein the gate regionis disposed about the vertical channel forming a continuous ringthereabout.
 29. The memory device, as set forth in claim 23, wherein thegate region is disposed about approximately half of the vertical channelforming a semi-annular ring thereabout.
 30. The memory device, as setforth in claim 23, wherein the gate region is coupled to a wordline of amemory array.
 31. The memory device, as set forth in claim 23, whereinthe storage device is coupled to the first source/drain.
 32. The memorydevice, as set forth in claim 31, comprising a bitline coupled to thesecond source/drain.
 33. The memory device, as set forth in claim 32,wherein the bitline is configured to form a ring around at least aportion of the channel such that the ring is directly adjacent to thesecond source/drain.
 34. The memory device, as set forth in claim 33,wherein the bitline is disposed about the vertical channel forming acontinuous ring thereabout.
 35. The memory device, as set forth in claim33, wherein the bitline is disposed about approximately half of thevertical channel forming a semi-annular ring thereabout.
 36. The memorydevice, as set forth in claim 33, wherein the bitline comprisespolysilicon.
 37. A processing system comprising: a microprocessor; and amemory device including: a non-volatile memory storage device; and anaccess transistor coupled to the storage device, said access transistorcomprises: a vertical channel coupled between a first source/drain and asecond source/drain; and a ring-like gate region disposed about at leasta portion of the vertical channel and configured to initiate conductionbetween the first source/drain and the second source/drain.
 38. Theprocessing system as set forth in claim 37, wherein the storage devicecomprises a magnetic tunnel junction.
 39. The processing system as setforth in claim 37, wherein the vertical channel comprises silicon (Si).40. The processing system as set forth in claim 37, wherein the gateregion comprises polysilicon.
 41. The processing system as set forth inclaim 37, wherein the gate region comprises a circular ring.
 42. Theprocessing system as set forth in claim 37, wherein the gate region isdisposed about the vertical channel forming a continuous ringthereabout.
 43. The processing system as set forth in claim 37, whereinthe gate region is disposed about approximately half of the verticalchannel forming a semi-annular ring thereabout.
 44. The processingsystem as set forth in claim 37, wherein the gate region is coupled to awordline of a memory array.
 45. The processing system, as set forth inclaim 37, wherein the storage device is coupled to the firstsource/drain.
 46. The processing system, as set forth in claim 45,comprising a bitline coupled to the second source/drain.
 47. Theprocessing system, as set forth in claim 46, wherein the bitline isconfigured to form a ring around at least a portion of the channel suchthat the ring is directly adjacent to the second source/drain.
 48. Theprocessing system, as set forth in claim 47, wherein the bitline isdisposed about the vertical channel forming a continuous ringthereabout.
 49. The processing system, as set forth in claim 47, whereinthe bitline is disposed about approximately half of the vertical channelforming a semi-annular ring thereabout.
 50. The processing system, asset forth in claim 47, wherein the bitline comprises polysilicon.
 51. Amethod of fabricating an integrated circuit comprising the acts of:forming a plurality of pillars in a substrate, the pillars extendingfrom a surface of the substrate and forming an array of rows andcolumns; disposing a first insulating layer over the surface of thesubstrate between each of the pillars; disposing a first layer ofconductive material over the first insulating layer; forming a firstdoped region in each of the plurality of pillars; etching the firstlayer of conductive material such that a ring is formed around at leasta portion of each of the pillars and wherein each of the rings in acolumn is electrically coupled to the adjacent rings in the column viathe conductive material; and forming a non-volatile memory bit on eachpillar.
 52. The method of fabricating an integrated circuit, as setforth in claim 51, wherein forming the plurality of pillars comprisesetching surrounding material to form the plurality of pillars in thesubstrate material.
 53. The method of fabricating an integrated circuit,as set forth in claim 51, wherein forming the plurality of pillarscomprises forming a plurality of pillars in silicon.
 54. The method offabricating an integrated circuit, as set forth in claim 53, whereinforming the plurality of pillars in silicon comprises forming aplurality of pillars in a heavily doped silicon.
 55. The method offabricating an integrated circuit, as set forth in claim 51, whereinforming a plurality of pillars comprises forming a plurality of verticalpillars extending perpendicular to the surface of the substrate.
 56. Themethod of fabricating an integrated circuit, as set forth in claim 51,wherein forming the first doped region comprises forming the first dopedregion by out-diffusion from the first layer of conductive material tothe substrate material.
 57. The method of fabricating an integratedcircuit, as set forth in claim 51, wherein forming the first dopedregion comprises forming the first doped region by ion implantation. 58.The method of fabricating an integrated circuit, as set forth in claim51, wherein disposing a first insulative layer comprises disposing alayer of oxide.
 59. The method of fabricating an integrated circuit, asset forth in claim 51, wherein disposing a first layer of conductivematerial comprises disposing a layer of polysilicon.
 60. The method offabricating an integrated circuit, as set forth in claim 51, whereinetching the first layer of conductive material comprises forming awordline in a memory array.
 61. The method of fabricating an integratedcircuit, as set forth in claim 51, wherein etching the first layer ofconductive material comprises forming a continuous annular ring abouteach of the pillars.
 62. The method of fabricating an integratedcircuit, as set forth in claim 51, wherein etching the first layer ofconductive material comprises forming a semi-annular ring about each ofthe pillars.
 63. The method of fabricating an integrated circuit, as setforth in claim 51, wherein etching the first layer of conductivematerial comprises forming a bitline in a memory array.
 64. The methodof fabricating an integrated circuit, as set forth in claim 63, furthercomprising the act of disposing a second insulative layer over the firstlayer of conductive material.
 65. The method of fabricating anintegrated circuit, as set forth in claim 64, further comprising the actof forming a gate oxide layer around each of the pillars such that thepillars are completely coated with the gate oxide layer from a pointcoincident with the second insulative layer to the end of the pillarfurthest from the surface of the substrate.
 66. The method offabricating an integrated circuit, as set forth in claim 65, furthercomprising the act of disposing a second layer of conductive materialover the second insulative layer.
 67. The method of fabricating anintegrated circuit, as set forth in claim 66, further comprising the actof etching the second layer of conductive material such that a secondring is formed around at least a portion of each of the pillars andwherein each of the rings in a row of the array is electrically coupledto the adjacent rings in the row by the conductive material.
 68. Themethod of fabricating an integrated circuit, as set forth in claim 67,wherein etching the second layer of conductive material comprisesforming a continuous annular ring about each of the pillars.
 69. Themethod of fabricating an integrated circuit, as set forth in claim 67,wherein etching the second layer of conductive material comprisesforming a semi-annular ring about each of the pillars.
 70. The method offabricating an integrated circuit, as set forth in claim 67, whereinetching the second layer of conductive material comprises forming awordline in a memory array.
 71. The method of fabricating an integratedcircuit, as set forth in claim 70, further comprising the act ofdisposing a third insulative layer on each of the second insulativelayer and second layer of conductive material, wherein the thirdinsulative layer is disposed to a thickness at least as high as each ofthe pillars.
 72. The method of fabricating an integrated circuit, as setforth in claim 71, further comprising the act of planarizing the thirdinsulative layer such that the top surface of each pillar is exposed.73. The method of fabricating an integrated circuit, as set forth inclaim 72, further comprising the act of forming a second doped region ineach of the plurality of pillars.
 74. The method of fabricating anintegrated circuit, as set forth in claim 73, wherein forming the seconddoped region comprises forming the second doped region by ionimplantation.
 75. The method of fabricating an integrated circuit, asset forth in claim 74, further comprising the act of forming a storagedevice on the surface of the third insulative layer such that thestorage device is electrically coupled to the second doped region. 76.The method of fabricating an integrated circuit, as set forth in claim75, wherein forming a storage device comprises fabricating a magnetictunnel junction.